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HD74ALVCH162721
3.3-V 20-bit Flip Flops with 3-state Outputs
REJ03D0044-0400Z (Previous ADE-205-184B (Z) ) Rev.4.00 Oct.02.2003
Description
The HD74ALVCH162721's twenty flip flops are edge triggered D-type flip flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs, provided that the clock enable (CLKEN) input is low. If CLKEN is high, no data is stored. A buffered output enable (OE) input can be used to place the twenty outputs in either a normal logic state (high or low level) or a high impedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly. The high impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. The output enable (OE) input does not affect the internal operation of the flip flops. Old data can be retained or new data can be entered while the outputs are in the high impedance state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up to 12 mA, include 26 resistors to reduce overshoot and undershoot.
Features
* * * * * * VCC = 2.3 V to 3.6 V Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25C) High output current 12 mA (@VCC = 3.0 V) Bus hold on data inputs eliminates the need for external pullup / pulldown resistors All outputs have equivalent 26 series resistors, so no external resistors are required.
Rev.4.00, Oct.02.2003, page 1 of 11
HD74ALVCH162721
Function Table
Inputs OE L L L L H CLKEN H L L L X CLK X L or H X D X H L X X Q0 *1 H L Q0 *1 Z Output Q
H : High level L : Low level X : Immaterial Z : High impedance : Low to high transition Note: 1. Output level before the indicated steady state input conditions were established.
Rev.4.00, Oct.02.2003, page 2 of 11
HD74ALVCH162721
Pin Arrangement
OE 1 Q1 2 Q2 3 GND 4 Q3 5 Q4 6 VCC 7 Q5 8 Q6 9 Q7 10 GND 11 Q8 12 Q9 13 Q10 14 Q11 15 Q12 16 Q13 17 GND 18 Q14 19 Q15 20 Q16 21 VCC 22 Q17 23 Q18 24 GND 25 Q19 26 Q20 27 NC 28
56 CLK 55 D1 54 D2 53 GND 52 D3 51 D4 50 VCC 49 D5 48 D6 47 D7 46 GND 45 D8 44 D9 43 D10 42 D11 41 D12 40 D13 39 GND 38 D14 37 D15 36 D16 35 VCC 34 D17 33 D18 32 GND 31 D19 30 D20 29 CLKEN
(Top view)
Rev.4.00, Oct.02.2003, page 3 of 11
HD74ALVCH162721
Absolute Maximum Ratings
Item Supply voltage Input voltage *1 Output voltage
*1, 2
Symbol VCC VI VO IIK IOK IO ICC or IGND PT Tstg
Ratings -0.5 to 4.6 -0.5 to 4.6 -0.5 to VCC +0.5 -50 50 50 100 1 -65 to 150
Unit V V V mA mA mA mA W C
Conditions
Input clamp current Output clamp current Continuous output current VCC, GND current / pin Maximum power dissipation at Ta = 55C (in still air) *3 Storage temperature Notes:
VI < 0 VO < 0 or VO > VCC VO = 0 to VCC TSSOP
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils.
Recommended Operating Conditions
Item Supply voltage Input voltage Output voltage High level output current Symbol VCC VI VO IOH Min 2.3 0 0 -- -- -- Low level output current IOL -- -- -- Input transition rise or fall rate Operating temperature t / v Ta 0 -40 Max 3.6 VCC VCC -6 -8 -12 6 8 12 10 85 ns / V C mA Unit V V V mA VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V Conditions
Note: Unused control inputs must be held high or low to prevent them from floating.
Rev.4.00, Oct.02.2003, page 4 of 11
HD74ALVCH162721
Logic Diagram
OE CLK CLKEN D1
1 56 29 55
CE C1 1D
2
Q1
To nineteen other channels
Rev.4.00, Oct.02.2003, page 5 of 11
HD74ALVCH162721
Electrical Characteristics
(Ta = -40 to 85C)
Item Input voltage Symbol VCC (V) *1 VIH VIL Output voltage VOH 2.3 to 2.7 2.7 to 3.6 2.3 to 2.7 2.7 to 3.6 2.3 2.3 3.0 2.7 3.0 VOL 2.3 2.3 3.0 2.7 3.0 Input current IIN IIN (hold) 3.6 2.3 2.3 3.0 3.0 3.6 Off state output current *2 IOZ Quiescent supply current ICC ICC 3.6 3.6 3.0 to 3.6 Min 1.7 2.0 -- -- 1.9 1.7 2.4 2.0 2.0 -- -- -- -- -- -- 45 -45 75 -75 -- -- -- -- Max -- -- 0.7 0.8 -- -- -- -- -- -- 0.2 0.4 0.55 0.55 0.6 0.8 5 -- -- -- -- 500 10 40 750 A A A A V IOH = -100 A IOH = -4 mA, VIH = 1.7 V IOH = -6 mA, VIH = 1.7 V IOH = -6 mA, VIH = 2.0 V IOH = -8 mA, VIH = 2.0 V IOH = -12 mA, VIH = 2.0 V IOL = 100 A IOL = 4 mA, VIL = 0.7 V IOL = 6 mA, VIL = 0.7 V IOL = 6 mA, VIL = 0.8 V IOL = 8 mA, VIL = 0.8 V IOL = 12 mA, VIL = 0.8 V VIN = VCC or GND VIN = 0.7 V VIN = 1.7 V VIN = 0.8 V VIN = 2.0 V VIN = 0 to 3.6 V VOUT = VCC or GND VIN = VCC or GND VIN = one input at (VCC-0.6) V, other inputs at VCC or GND Unit V Test Conditions
Min to Max VCC-0.2
Min to Max --
Notes: 1. For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. 2. For I/O ports, the parameter IOZ includes the input leakage current.
Rev.4.00, Oct.02.2003, page 6 of 11
HD74ALVCH162721
Switching Characteristics
(Ta = -40 to 85C)
Item Maximum clock frequency Symbol VCC (V) fmax 2.50.2 2.7 3.30.3 Propagation delay time tPLH tPHL Output enable time tZH tZL Output disable time tHZ tLZ Setup time tsu 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 Hold time th 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 Pulse width tw 2.50.2 2.7 3.30.3 Input capacitance Output capacitance CIN CO 3.3 3.3 Min 150 150 150 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 4.0 3.6 3.1 3.4 3.1 2.7 0 0 0 0 0 0 3.3 3.3 3.3 -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 3.5 7.0 Max -- -- -- 6.7 6.2 5.3 7.2 7.0 5.8 6.3 5.4 5.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- pF pF ns CLKEN after CLK ns Data after CLK CLKEN before CLK ns Data before CLK ns OE Q ns OE Q ns CLK Q Unit MHz FROM (Input) TO (Output)
Rev.4.00, Oct.02.2003, page 7 of 11
HD74ALVCH162721
* Test Circuit
See under table 500 S1 OPEN
*1
GND 500
C L = 50 pF
Load Circuit for Outputs Symbol t PLH / t PHL t su / t h / t w t ZH/ t HZ t ZL / t LZ
Vcc=2.50.2V Vcc=2.7V, 3.30.3V
OPEN GND 4.6 V
OPEN GND 6.0 V
Note: 1. C L includes probe and jig capacitance.
Rev.4.00, Oct.02.2003, page 8 of 11
HD74ALVCH162721
* Waveforms - 1
tr 90 %
90 % Vref
tf
VIH
10 %
Input
10 %
Vref
t PLH
t PHL
GND
VOH
Output Vref Vref
VOL
* Waveforms - 2
tr 90 %
VIH GND VIH
Timing Input
10 % tsu
Vref
th
Data Input
Vref
Vref GND
tw
VIH Input Vref Vref GND
Rev.4.00, Oct.02.2003, page 9 of 11
HD74ALVCH162721
* Waveforms - 3
90 % Vref
tf
tr
90 %
VIH GND VOH1
Output Control
Vref
10 % t ZL
10 %
t LZ
Vref
Waveform - A
VOL + 0.3 V
t HZ
t ZH
Waveform - B Vref
VOL VOH
VOL1
VOH - 0.3 V
TEST VIH Vref VOH1 VOL1
Vcc=2.50.2V
Vcc=2.7V, 3.30.3V
2.3 V
2.7 V
1.2 V 2.3 V GND
1.5 V 3.0 V
GND
Notes: 1. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Zo = 50 , tr 2.5 ns, tf 2.5 ns. 2. Waveform - A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform - B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement.
Rev.4.00, Oct.02.2003, page 10 of 11
HD74ALVCH162721
Package Dimensions
As of January, 2003
14.0 14.2 Max 56 29 6.10
Unit: mm
1 *0.19 0.05
0.50 0.08 M
28
1.0 8.10 0.20 0 - 8 *0.15 0.05 0.10 0.05 0.50 0.1
0.65 Max
1.20 Max
0.10
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
TTP-56DAV -- -- 0.23 g
Rev.4.00, Oct.02.2003, page 11 of 11
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